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<a href="uc3c_2pll_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 
<a name="l00038"></a>00038 <span class="preprocessor">#ifndef CHIP_PLL_H_INCLUDED</span>
<a name="l00039"></a>00039 <span class="preprocessor"></span><span class="preprocessor">#define CHIP_PLL_H_INCLUDED</span>
<a name="l00040"></a>00040 <span class="preprocessor"></span>
<a name="l00041"></a>00041 <span class="preprocessor">#ifdef __cplusplus</span>
<a name="l00042"></a>00042 <span class="preprocessor"></span><span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {
<a name="l00043"></a>00043 <span class="preprocessor">#endif</span>
<a name="l00044"></a>00044 <span class="preprocessor"></span>
<a name="l00045"></a>00045 <span class="comment">// Bugzilla #11801</span>
<a name="l00046"></a>00046 <span class="preprocessor">#ifdef AVR32_SCIF_PLL_VCO_RANGE0_MAX_FREQ</span>
<a name="l00047"></a>00047 <span class="preprocessor"></span><span class="preprocessor">#undef AVR32_SCIF_PLL_VCO_RANGE0_MAX_FREQ</span>
<a name="l00048"></a>00048 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00049"></a><a class="code" href="uc3c_2pll_8h.html#a07643f13da0314cb5324f12c11f326dd">00049</a> <span class="preprocessor"></span><span class="preprocessor">#define AVR32_SCIF_PLL_VCO_RANGE0_MAX_FREQ   240000000</span>
<a name="l00050"></a>00050 <span class="preprocessor"></span><span class="preprocessor">#ifdef AVR32_SCIF_PLL_VCO_RANGE0_MIN_FREQ</span>
<a name="l00051"></a>00051 <span class="preprocessor"></span><span class="preprocessor">#undef AVR32_SCIF_PLL_VCO_RANGE0_MIN_FREQ</span>
<a name="l00052"></a>00052 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00053"></a><a class="code" href="uc3c_2pll_8h.html#aabe42b8f766d0b3a02385d4c04494810">00053</a> <span class="preprocessor"></span><span class="preprocessor">#define AVR32_SCIF_PLL_VCO_RANGE0_MIN_FREQ   160000000</span>
<a name="l00054"></a>00054 <span class="preprocessor"></span><span class="preprocessor">#ifdef AVR32_SCIF_PLL_VCO_RANGE1_MAX_FREQ</span>
<a name="l00055"></a>00055 <span class="preprocessor"></span><span class="preprocessor">#undef AVR32_SCIF_PLL_VCO_RANGE1_MAX_FREQ</span>
<a name="l00056"></a>00056 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00057"></a><a class="code" href="uc3c_2pll_8h.html#ac443c8c74126291df314757d411a14f5">00057</a> <span class="preprocessor"></span><span class="preprocessor">#define AVR32_SCIF_PLL_VCO_RANGE1_MAX_FREQ   180000000</span>
<a name="l00058"></a>00058 <span class="preprocessor"></span><span class="preprocessor">#ifdef AVR32_SCIF_PLL_VCO_RANGE1_MIN_FREQ</span>
<a name="l00059"></a>00059 <span class="preprocessor"></span><span class="preprocessor">#undef AVR32_SCIF_PLL_VCO_RANGE1_MIN_FREQ</span>
<a name="l00060"></a>00060 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
<a name="l00061"></a><a class="code" href="uc3c_2pll_8h.html#a39aa078b560b8e913eb40001f6a857ca">00061</a> <span class="preprocessor"></span><span class="preprocessor">#define AVR32_SCIF_PLL_VCO_RANGE1_MIN_FREQ   80000000</span>
<a name="l00062"></a>00062 <span class="preprocessor"></span>
<a name="l00067"></a><a class="code" href="group__pll__group.html#ga3a7cd8f570834e0f208037619b798aef">00067</a> <span class="preprocessor">#define PLL_MAX_STARTUP_CYCLES    ((1 &lt;&lt; AVR32_SCIF_PLL_PLLCOUNT_SIZE) - 1)</span>
<a name="l00068"></a><a class="code" href="group__pll__group.html#ga23ebd75638f609ce613b82e773ea48a5">00068</a> <span class="preprocessor"></span><span class="preprocessor">#define NR_PLLS                   2</span>
<a name="l00069"></a>00069 <span class="preprocessor"></span>
<a name="l00073"></a><a class="code" href="group__pll__group.html#ga3778ecbe3fb3e8480ce23312a613a0aa">00073</a> <span class="preprocessor">#define PLL_TIMEOUT_MS    \</span>
<a name="l00074"></a>00074 <span class="preprocessor">        div_ceil(1000 * (PLL_MAX_STARTUP_CYCLES * 2), OSC_RCSYS_MIN_HZ)</span>
<a name="l00075"></a>00075 <span class="preprocessor"></span>
<a name="l00080"></a><a class="code" href="group__pll__group.html#ga58acd4425beaa32dad5ccffa073cb0a5">00080</a> <span class="preprocessor">#define PLL_MIN_HZ                40000000</span>
<a name="l00081"></a><a class="code" href="group__pll__group.html#gaeced77fb7ec635ab33085a71a0c15227">00081</a> <span class="preprocessor"></span><span class="preprocessor">#define PLL_MAX_HZ                240000000</span>
<a name="l00082"></a>00082 <span class="preprocessor"></span>
<a name="l00084"></a>00084 
<a name="l00085"></a>00085 
<a name="l00086"></a><a class="code" href="group__pll__group.html#ga03717c32c87c59df4b94a4233a5c2e3e">00086</a> <span class="preprocessor">#define PLL_OPT_VCO_RANGE_LOW     0</span>
<a name="l00087"></a>00087 <span class="preprocessor"></span>
<a name="l00088"></a><a class="code" href="group__pll__group.html#ga0ab4eb3395991501ba1c8aa8a7c606be">00088</a> <span class="preprocessor">#define PLL_OPT_OUTPUT_DIV        1</span>
<a name="l00089"></a>00089 <span class="preprocessor"></span>
<a name="l00090"></a><a class="code" href="group__pll__group.html#gaa2d0c945bda195002b421eb79d2c87ca">00090</a> <span class="preprocessor">#define PLL_OPT_WBM_DISABLE       2</span>
<a name="l00091"></a>00091 <span class="preprocessor"></span>
<a name="l00092"></a><a class="code" href="group__pll__group.html#gae74457d5b4073fdb82cb6b9f3d8b76e2">00092</a> <span class="preprocessor">#define PLL_NR_OPTIONS            AVR32_SCIF_PLL_PLLOPT_SIZE</span>
<a name="l00093"></a>00093 <span class="preprocessor"></span>
<a name="l00094"></a><a class="code" href="group__pll__group.html#ga49eaeabf6add7c1be4000c77cb8b2bff">00094</a> <span class="preprocessor">#define PLL_VCO_LOW_THRESHOLD     ((AVR32_SCIF_PLL_VCO_RANGE0_MIN_FREQ         \</span>
<a name="l00095"></a>00095 <span class="preprocessor">                + AVR32_SCIF_PLL_VCO_RANGE1_MAX_FREQ) / 2)</span>
<a name="l00096"></a>00096 <span class="preprocessor"></span>
<a name="l00097"></a>00097 
<a name="l00098"></a>00098 <span class="preprocessor">#ifndef __ASSEMBLY__</span>
<a name="l00099"></a>00099 <span class="preprocessor"></span>
<a name="l00100"></a>00100 <span class="preprocessor">#include &lt;avr32/io.h&gt;</span>
<a name="l00101"></a>00101 <span class="preprocessor">#include &lt;osc.h&gt;</span>
<a name="l00102"></a>00102 <span class="preprocessor">#include &lt;stdbool.h&gt;</span>
<a name="l00103"></a>00103 <span class="preprocessor">#include &lt;stdint.h&gt;</span>
<a name="l00104"></a>00104 
<a name="l00105"></a><a class="code" href="group__pll__group.html#gacfb06d8fc0ffbe934077438884ae697f">00105</a> <span class="keyword">enum</span> <a class="code" href="group__pll__group.html#gacfb06d8fc0ffbe934077438884ae697f" title="PLL clock source.">pll_source</a> {
<a name="l00106"></a><a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa060f32d7388cf128f527739090aa4217">00106</a>         <a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa060f32d7388cf128f527739090aa4217" title="Oscillator 0.">PLL_SRC_OSC0</a>            = 0,    
<a name="l00107"></a><a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa28e003235f43b85c6ee49bbe81b67218">00107</a>         <a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa28e003235f43b85c6ee49bbe81b67218" title="Oscillator 1.">PLL_SRC_OSC1</a>            = 1,    
<a name="l00108"></a><a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa87507b481d2c92b721d802a5ae6cc8a5">00108</a>         <a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa87507b481d2c92b721d802a5ae6cc8a5" title="8MHz/1MHz RC oscillator">PLL_SRC_RC8M</a>            = 2,    
<a name="l00109"></a><a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa5020b47784b860efae2c423d33999dcc">00109</a>         <a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa5020b47784b860efae2c423d33999dcc" title="Number of PLL sources.">PLL_NR_SOURCES</a>,                 
<a name="l00110"></a>00110 };
<a name="l00111"></a>00111 
<a name="l00112"></a><a class="code" href="structpll__config.html">00112</a> <span class="keyword">struct </span><a class="code" href="structpll__config.html" title="Hardware-specific representation of PLL configuration.">pll_config</a> {
<a name="l00113"></a><a class="code" href="structpll__config.html#a34089a7ab6c1536ae2e8d6d8e2929ac5">00113</a>         uint32_t <a class="code" href="structpll__config.html#a34089a7ab6c1536ae2e8d6d8e2929ac5">ctrl</a>;
<a name="l00114"></a>00114 };
<a name="l00115"></a>00115 
<a name="l00116"></a><a class="code" href="group__pll__group.html#ga16c8db5e3f1a2c759a88371120579c4d">00116</a> <span class="preprocessor">#define pll_get_default_rate(pll_id)                                           \</span>
<a name="l00117"></a>00117 <span class="preprocessor">        ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE)                            \</span>
<a name="l00118"></a>00118 <span class="preprocessor">                        * CONFIG_PLL##pll_id##_MUL)                            \</span>
<a name="l00119"></a>00119 <span class="preprocessor">                        / CONFIG_PLL##pll_id##_DIV)</span>
<a name="l00120"></a>00120 <span class="preprocessor"></span>
<a name="l00121"></a>00121 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> pll_config_set_option(<span class="keyword">struct</span> <a class="code" href="structpll__config.html" title="Hardware-specific representation of PLL configuration.">pll_config</a> *cfg,
<a name="l00122"></a>00122                 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> option)
<a name="l00123"></a>00123 {
<a name="l00124"></a>00124         Assert(option &lt; <a class="code" href="group__pll__group.html#gae74457d5b4073fdb82cb6b9f3d8b76e2" title="Number of PLL option bits.">PLL_NR_OPTIONS</a>);
<a name="l00125"></a>00125 
<a name="l00126"></a>00126         cfg-&gt;<a class="code" href="structpll__config.html#a34089a7ab6c1536ae2e8d6d8e2929ac5">ctrl</a> |= 1U &lt;&lt; (AVR32_SCIF_PLLOPT + option);
<a name="l00127"></a>00127 }
<a name="l00128"></a>00128 
<a name="l00129"></a>00129 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> pll_config_clear_option(<span class="keyword">struct</span> <a class="code" href="structpll__config.html" title="Hardware-specific representation of PLL configuration.">pll_config</a> *cfg,
<a name="l00130"></a>00130                 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> option)
<a name="l00131"></a>00131 {
<a name="l00132"></a>00132         Assert(option &lt; <a class="code" href="group__pll__group.html#gae74457d5b4073fdb82cb6b9f3d8b76e2" title="Number of PLL option bits.">PLL_NR_OPTIONS</a>);
<a name="l00133"></a>00133 
<a name="l00134"></a>00134         cfg-&gt;<a class="code" href="structpll__config.html#a34089a7ab6c1536ae2e8d6d8e2929ac5">ctrl</a> &amp;= ~(1U &lt;&lt; (AVR32_SCIF_PLLOPT + option));
<a name="l00135"></a>00135 }
<a name="l00136"></a>00136 
<a name="l00141"></a>00141 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> pll_config_init(<span class="keyword">struct</span> <a class="code" href="structpll__config.html" title="Hardware-specific representation of PLL configuration.">pll_config</a> *cfg,
<a name="l00142"></a>00142                 <span class="keyword">enum</span> <a class="code" href="group__pll__group.html#gacfb06d8fc0ffbe934077438884ae697f" title="PLL clock source.">pll_source</a> src, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> div, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> mul)
<a name="l00143"></a>00143 {
<a name="l00144"></a>00144         uint32_t vco_hz;
<a name="l00145"></a>00145 
<a name="l00146"></a>00146         Assert(src &lt; <a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa5020b47784b860efae2c423d33999dcc" title="Number of PLL sources.">PLL_NR_SOURCES</a>);
<a name="l00147"></a>00147 
<a name="l00148"></a>00148         <span class="comment">/* Calculate internal VCO frequency */</span>
<a name="l00149"></a>00149         vco_hz = osc_get_rate(src) * mul;
<a name="l00150"></a>00150         vco_hz /= div;
<a name="l00151"></a>00151         Assert(vco_hz &gt;= <a class="code" href="group__pll__group.html#ga58acd4425beaa32dad5ccffa073cb0a5" title="Minimum frequency that the PLL can generate.">PLL_MIN_HZ</a>);
<a name="l00152"></a>00152         Assert(vco_hz &lt;= <a class="code" href="group__pll__group.html#gaeced77fb7ec635ab33085a71a0c15227" title="Maximum frequency that the PLL can generate.">PLL_MAX_HZ</a>);
<a name="l00153"></a>00153 
<a name="l00154"></a>00154         cfg-&gt;<a class="code" href="structpll__config.html#a34089a7ab6c1536ae2e8d6d8e2929ac5">ctrl</a> = 0;
<a name="l00155"></a>00155 
<a name="l00156"></a>00156         <span class="comment">/* Bring the internal VCO frequency up to the minimum value */</span>
<a name="l00157"></a>00157         <span class="keywordflow">if</span> ((vco_hz &lt; <a class="code" href="group__pll__group.html#ga58acd4425beaa32dad5ccffa073cb0a5" title="Minimum frequency that the PLL can generate.">PLL_MIN_HZ</a> * 2) &amp;&amp; (mul &lt;= 8)) {
<a name="l00158"></a>00158                 mul *= 2;
<a name="l00159"></a>00159                 vco_hz *= 2;
<a name="l00160"></a>00160                 pll_config_set_option(cfg, <a class="code" href="group__pll__group.html#ga0ab4eb3395991501ba1c8aa8a7c606be" title="Divide output frequency by two.">PLL_OPT_OUTPUT_DIV</a>);
<a name="l00161"></a>00161         }
<a name="l00162"></a>00162 
<a name="l00163"></a>00163         <span class="comment">/* Set VCO frequency range according to calculated value */</span>
<a name="l00164"></a>00164         <span class="keywordflow">if</span> (vco_hz &lt; <a class="code" href="group__pll__group.html#ga49eaeabf6add7c1be4000c77cb8b2bff" title="The threshold under which to set the PLL_OPT_VCO_RANGE_LOW option.">PLL_VCO_LOW_THRESHOLD</a>)
<a name="l00165"></a>00165                 pll_config_set_option(cfg, <a class="code" href="group__pll__group.html#ga03717c32c87c59df4b94a4233a5c2e3e" title="VCO frequency range is 80-180 MHz (160-240 MHz if unset).">PLL_OPT_VCO_RANGE_LOW</a>);
<a name="l00166"></a>00166 
<a name="l00167"></a>00167         Assert(mul &gt; 2 &amp;&amp; mul &lt;= 16);
<a name="l00168"></a>00168         Assert(div &gt; 0 &amp;&amp; div &lt;= 15);
<a name="l00169"></a>00169 
<a name="l00170"></a>00170         cfg-&gt;<a class="code" href="structpll__config.html#a34089a7ab6c1536ae2e8d6d8e2929ac5">ctrl</a> |= ((mul - 1) &lt;&lt; AVR32_SCIF_PLLMUL)
<a name="l00171"></a>00171                 | (div &lt;&lt; AVR32_SCIF_PLLDIV)
<a name="l00172"></a>00172                 | (<a class="code" href="group__pll__group.html#ga3a7cd8f570834e0f208037619b798aef" title="Maximum PLL startup time in number of slow clock cycles.">PLL_MAX_STARTUP_CYCLES</a> &lt;&lt; AVR32_SCIF_PLLCOUNT)
<a name="l00173"></a>00173                 | (src &lt;&lt; AVR32_SCIF_PLLOSC);
<a name="l00174"></a>00174 }
<a name="l00175"></a>00175 
<a name="l00176"></a><a class="code" href="group__pll__group.html#ga2b9ba9ce6a7290303f6e8d41191fd0d8">00176</a> <span class="preprocessor">#define pll_config_defaults(cfg, pll_id)                                       \</span>
<a name="l00177"></a>00177 <span class="preprocessor">        pll_config_init(cfg,                                                   \</span>
<a name="l00178"></a>00178 <span class="preprocessor">                        CONFIG_PLL##pll_id##_SOURCE,                           \</span>
<a name="l00179"></a>00179 <span class="preprocessor">                        CONFIG_PLL##pll_id##_DIV,                              \</span>
<a name="l00180"></a>00180 <span class="preprocessor">                        CONFIG_PLL##pll_id##_MUL)</span>
<a name="l00181"></a>00181 <span class="preprocessor"></span>
<a name="l00182"></a>00182 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> pll_config_read(<span class="keyword">struct</span> <a class="code" href="structpll__config.html" title="Hardware-specific representation of PLL configuration.">pll_config</a> *cfg, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> pll_id)
<a name="l00183"></a>00183 {
<a name="l00184"></a>00184         Assert(pll_id &lt; <a class="code" href="group__pll__group.html#ga23ebd75638f609ce613b82e773ea48a5" title="Number of on-chip PLLs.">NR_PLLS</a>);
<a name="l00185"></a>00185 
<a name="l00186"></a>00186         cfg-&gt;<a class="code" href="structpll__config.html#a34089a7ab6c1536ae2e8d6d8e2929ac5">ctrl</a> = AVR32_SCIF.pll[pll_id];
<a name="l00187"></a>00187 }
<a name="l00188"></a>00188 
<a name="l00189"></a>00189 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="group__pll__group.html#gaeee0be729bfa596c973cf6f725a89d45" title="Activate the configuration cfg on pll_id.">pll_config_write</a>(<span class="keyword">const</span> <span class="keyword">struct</span> <a class="code" href="structpll__config.html" title="Hardware-specific representation of PLL configuration.">pll_config</a> *cfg, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> pll_id);
<a name="l00190"></a>00190 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="group__pll__group.html#gaede6e280289cb0759af0f5a34f5a627f" title="Activate the configuration cfg and enable PLL pll_id.">pll_enable</a>(<span class="keyword">const</span> <span class="keyword">struct</span> <a class="code" href="structpll__config.html" title="Hardware-specific representation of PLL configuration.">pll_config</a> *cfg, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> pll_id);
<a name="l00191"></a>00191 <span class="keyword">extern</span> <span class="keywordtype">void</span> <a class="code" href="group__pll__group.html#ga9b369b5f673b10a6adf14cd3c9fea5ad" title="Disable the PLL identified by pll_id.">pll_disable</a>(<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> pll_id);
<a name="l00192"></a>00192 
<a name="l00193"></a>00193 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">bool</span> pll_is_locked(<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> pll_id)
<a name="l00194"></a>00194 {
<a name="l00195"></a>00195         Assert(pll_id &lt; <a class="code" href="group__pll__group.html#ga23ebd75638f609ce613b82e773ea48a5" title="Number of on-chip PLLs.">NR_PLLS</a>);
<a name="l00196"></a>00196 
<a name="l00197"></a>00197         <span class="keywordflow">return</span> !!(AVR32_SCIF.pclksr &amp; (1U &lt;&lt; (AVR32_SCIF_PLL0_LOCK + pll_id)));
<a name="l00198"></a>00198 }
<a name="l00199"></a>00199 
<a name="l00200"></a>00200 <span class="keyword">static</span> <span class="keyword">inline</span> <span class="keywordtype">void</span> pll_enable_source_sync(<span class="keyword">enum</span> <a class="code" href="group__pll__group.html#gacfb06d8fc0ffbe934077438884ae697f" title="PLL clock source.">pll_source</a> src)
<a name="l00201"></a>00201 {
<a name="l00202"></a>00202         <span class="keywordflow">switch</span> (src) {
<a name="l00203"></a>00203         <span class="keywordflow">case</span> <a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa060f32d7388cf128f527739090aa4217" title="Oscillator 0.">PLL_SRC_OSC0</a>:
<a name="l00204"></a>00204                 osc_enable(src);
<a name="l00205"></a>00205                 osc_wait_ready(src);
<a name="l00206"></a>00206                 <span class="keywordflow">break</span>;
<a name="l00207"></a>00207 
<a name="l00208"></a>00208         <span class="keywordflow">case</span> <a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa28e003235f43b85c6ee49bbe81b67218" title="Oscillator 1.">PLL_SRC_OSC1</a>:
<a name="l00209"></a>00209                 osc_enable(src);
<a name="l00210"></a>00210                 osc_wait_ready(src);
<a name="l00211"></a>00211                 <span class="keywordflow">break</span>;
<a name="l00212"></a>00212 
<a name="l00213"></a>00213         <span class="keywordflow">case</span> <a class="code" href="group__pll__group.html#ggacfb06d8fc0ffbe934077438884ae697fa87507b481d2c92b721d802a5ae6cc8a5" title="8MHz/1MHz RC oscillator">PLL_SRC_RC8M</a>:
<a name="l00214"></a>00214                 osc_enable(<a class="code" href="group__osc__group.html#ga37f1cac41a51005a5acdb308f2258bd0" title="Internal 8 MHz RC oscillator.">OSC_ID_RC8M</a>);
<a name="l00215"></a>00215                 osc_wait_ready(<a class="code" href="group__osc__group.html#ga37f1cac41a51005a5acdb308f2258bd0" title="Internal 8 MHz RC oscillator.">OSC_ID_RC8M</a>);
<a name="l00216"></a>00216                 <span class="keywordflow">break</span>;
<a name="l00217"></a>00217 
<a name="l00218"></a>00218         <span class="keywordflow">default</span>:
<a name="l00219"></a>00219                 <span class="comment">// unhandled_case(src);</span>
<a name="l00220"></a>00220                 <span class="keywordflow">break</span>;
<a name="l00221"></a>00221         }
<a name="l00222"></a>00222 }
<a name="l00223"></a>00223 
<a name="l00224"></a>00224 <span class="preprocessor">#endif </span><span class="comment">/* __ASSEMBLY__ */</span>
<a name="l00225"></a>00225 
<a name="l00227"></a>00227 
<a name="l00228"></a>00228 <span class="preprocessor">#ifdef __cplusplus</span>
<a name="l00229"></a>00229 <span class="preprocessor"></span>}
<a name="l00230"></a>00230 <span class="preprocessor">#endif</span>
<a name="l00231"></a>00231 <span class="preprocessor"></span>
<a name="l00232"></a>00232 <span class="preprocessor">#endif </span><span class="comment">/* CHIP_PLL_H_INCLUDED */</span>
</pre></div></div>
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